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General Information

O-RAN Distributed Unit Low Layers (
ODULOW
O-DU LOW)
PTL
Zhimin Yuan
@Farias Luis
Summary
Focus on L1 functional
blocks 
 development according to O-RAN WGs and 3GPP specification.
Project
o-du, o-du/l2, o-du/phy
, o-du/sim

Weekly Meetings

TBD, anyone is interested in O-DU Low project, would like to get more information, would like to know how to participant, please no hesitate to contact zhimin.yuan@intel or raise any questions through this wiki page.

Quick Explore:

Below link will help you have a quick explore

View current code contribution through web:

https://gerrit.o-ran-sc.org/r/gitweb?p=o-du/phy.git;a=tree

Explore the Documentation:

https://docs.o-ran-sc.org/en/latest/projects.html#o-ran-distributed-unit-low-layers-odulow


 Quick Explore
General Introduction
The project include two parts contributions
part 1: O-RAN FH interface lib, FAPI TM lib and WLS lib. O-RAN FH interface lib which follow O-RAN WG4 interface to implement O-RAN radio interface from DU end, WLS and FAPI TM is the interface implementation between O-DU low and O-DU High. 
part 2: L1 binary along with one set of uses cases which were performed with test MAC application.
With above parts, below O-RAN network functions can be verified with different data flow to meet your different purpose:
  • data flow 1: FH lib UT, FH lib had it's own test framework, which includes one test app to simulator the l1 and test RU to simulator the RU, between test app and test RU, data was exchanged follow O-RAN WG4 C/U/S plane spec. there are multiple use cases that are defined with variant numerology and bandwidth.   
  • data flow 2: RRU interface UT, the test app and FH lib can also be used to test real RRU with simulated L1 data connecting to SA/SG  
  • data flow 3: testmac timer: L1 binary and test mac timer mode was provided to verify the FAPI interface with full L1 pipeline/functionalities , it also can be used to verify the HW platform supportive of the L1 SW with proper capabilities.  
  • data flow 4: testmac radio:  With full L1 pipeline integrated FH lib, this data flow can be used to verify the RRU with full L1 pipeline. 
  • data flow 5: E2E open source: together with other open source project in OSC, E2E data flow can be verified, please go to Integration and Testing and Requirements and Software Architecture Committee Home for detail E2E integration current status and plan.
Image Added 
below picture shows the architecture and the interface of O-DU low. this project 
General Architecture
Current L1 functional development 
 mainly focus on the open interface development so far, three interfaces will be involved to interact with 
 L1  as below
L1.
image2020-2-11_17-41-16.pngImage Added
Interfaces:
Image Removed
Minutes:
Action Items:
  1. Zhimin will provide
- Model number of FPGA card such that Ray can invite the company to join this project
- A list of job items for DPDK xRAN. Ray can pass the information to his colleague, Prof. Shen, for evaluation
 2. Sam has to check the supporting of NIC (and confirm it with Zhimin) and IEEE 1588
 3. Ray's team will figure out how to reuse the API document generated  by Doxygen and convert it to RST format
  • Interface between L1 and Front haul, it will adopt the WG4 specification for the CUS plane communication. 
  • Interface between O-DU Low and O-DU High, FAPI interface will be adopt according to WG8 AAL specification.
  • Interface between O-DU Low and accelerator, it's the hot topic in WG6 now,  DPDK BBDev was adopted as 
     previous 
    current design, it 
     will 
     follow the 
     WG6 definition after WG6 specification is finalized. 
For amber release, O-RAN FH library was contributed by Intel as seed code, BBDev API was already open source in DPDK community, please find detail API information in http://doc.dpdk.org/api/rte__bbdev_8h.html, FAPI API is under development.
O-RAN FH Lib is developed according to the O-RAN WG4 specification. It performs communication between the O-DU and RU and consists of multiple HW and SW components. Logical representation of HW and SW components is shown as below diagram:
Image Removed
From the hardware perspective, two networking ports are used to communicate to the Front Haul and Back (Mid) Haul network as well as to receive PTP synchronization. The system timer is used to provide “sense” of time to the gNB application.
From Software perspective the following components are used:
  • Linux PTP provides synchronization of system timer to GPS time.
    • Ptp4l is used to synchronize oscillator on Network Interface Controller (NIC) to PTP GM.
    • Phc2sys is used to synchronize system timer to oscillator on NIC.
  • DPDK to provide interface to Ethernet port.
  • O-RAN FH library is built on top of DPDK to perform U-plane and C-plane functionality according to the O-RAN WG4 specification.
  • 5G NR PHY(L1) uses the O-RAN FH library to access interface to RU. The interface between O-RAN FH library and 5G NR PHY is defined to communicate TTI event, symbol time, C-plane information as well as IQ sample data.
  • 5G NR PHY communicates with L2+ application using the set of MAC/PHY APIs and the shared memory interface defined as WLS.
  • L2+ in turn can use Back (Mid) Haul networking port to connect to CU unit in context of 3GPP specification.
Weekly meeting:
Now it's mainly ad-hoc meeting, record as below:
date: Mar.16Attendees:
Intel: Zhimin
NTUST: Ray, Prof. Chung-An Shen, Prof. Chin-Ya Huang
Minutes:
Action Items:
- Zhimin provide
    - Share the figure for testing architecture
    - A list of job items to be done for DPDK xRAN
    - Provide O-RAN FH architecture document for Prof. Shen for reference. Ray's team may help to convert it to RST format
    - Provide the model number for O-RU simulator
- Prof. Shen, check the available resource and determine the job
- Ray: 
    - AAEON can only provide one server for O-CU+O-DU.
    - Write a mail to Viavi for testing equipment
date: Mar.8Attendees:
Intel: Zhimin
NTUST: Ray, Prof. 
AAeon: SamChen; FredyHsu; EyckNi; 
  • O-RAN WG6 specification.